Polyphase inverter



April 9, 1968 J. w. BATES 3,377,539

DoLYPHASE /INVERTER Original Filed Oct. l2, 1962 3 Sheets-Sheet f:

64, 6,8 A510 1 4 75a i@ 644, a 54d .lg A 73 0 L N e@ 5w 'wgb 5? n 13e 58T \6jalJ .90a

INVENTOR Jam@ z/f, 3d@

April 9, 1968 J. W. BATES POLYPHASE INVERTER Original Filed oct. 12, 19@

5 Sheets-Sheet I5 United States Patent O 3,377,539 POLYPHASE INVERTERJames W. Bates, Palos Verdes, Calif., assigner to Gulton Industries,Inc., Metuchen, NJ., a corporation of New Jersey Continuation ofapplication Ser. No. 230,078, Oct. 12, 1962. This application June 29,1966, Ser. No. 562,937 6 Claims. (Cl. 321-5) This application is acontinuation of Ser. No. 230,078, filed Oct. 12, 1962, now abandoned.

This invention relates to circuits for converting direct current `(DC)to alternating current (AC). Such circuits are commonly referred to asinverter circuits. More particularly the invention relates .to aninverter circuit for converting direct current to polyphase alternatingcurrent.

It is old and well known in the art to produce Aan alternating signalfrom direct current by means of an inverter circuit comprising an outputtransformer having primary and secondary windings and switch means foralternately A related object of the present invention is to provide apolyphase inverter system as just described wherein the invertersutilize electronic switches, most advantageously transistors and/orgated diodes.

Another object of the present invention is to provide a polyphaseinverter system as described wherein the inverter system includes asquare wave oscillator inverter circuit for each signal phase, andwherein the oscillator circuits are synchronized in a manner whichprovides Aprecisely phased AC output signals.

Still another object of the present invention is to provide a polyphaseinverter system as just described wherein the square wave oscillatorinverter circuits are synchronized from a common oscillator and thedesired phasing between the output signals is maintained despite minorvariations in the frequency of the common oscillator.

A further object of the present invention is to provide a polyphaseinverter system as above described which is capable of supplyingpolyphase power to relatively heavy loads.

An over-al1 object of the present invention is to provide a polyphaseinverter system which preferably accomplishes all of the above-mentionedobjectives utilizing a minimum of parts to reduce costs and improvecircuit reliability.

In accordance with one aspect of the present invention,

la separate inverter circuit is provided for each of the desired outputAC signals, one of the inverter .circuits being referred to as a masterinverter circuit and the other inverter circuits being referred to asslave inverter circuits. In the case where the inverter system is toproduce three signals at a given frequency spaced 120 apart, there willbe three inverter circuits operating at a relative yphase displacementof 60 or 120 (the inversion of 'the 60 phase signal produces the 240phase signal). In a manner to be explained, the inverter circuits aresynchronized from a common oscillator preferably energized `from thesource of direct current (DC) voltage to provide a synchronizing signalhaving a frequency preferably which is an integral number of times.higher than lthe frequency of the desired output signal. For example,

`output frequency.

3,377,539 Patented Apr. 9, 1968 "ice .2 assuming an output signalfrequency of 400 cycles per second, the common .oscillator may `have afrequency of, say, 1200 cycles per second. The switch means of eachinverter circuit, which alternately couples the source of direct`current voltage in opposite ,directions through the primary winding ofthe output transformer thereof upon successive actuations of the switchmeans, is controlled by switch control means which actuate the switchmeans of the various inverter circuits in a predetermined time sequenceand at a frequency which producesfthe desired The switch control meansreferred to preferably includes means associated with .each slaveinverter circuit which means is responsive tothe reversal of the ACsignal in the output ofthe inverter circuit which operates irrimediatelyahead of it by preparing the associated switch means for subsequentactuation by ythe output of the common oscillator. The master invertercircuit includes means for effecting successive actuation of theassociated switch means at intervals encompassing a predetermined numberof .cycles ofthe output ofthe common oscillator. In the exampleinvolved, .the interval between successive actuations of the switch.means ofthe master inverter circuit, which represent 180 of the desiredoutput frequency, amounts to one and one-half cycles of the exemplary1200 master oscillator frequency. In effect, the

master inverter circuit acts a a circuit which divides the frequency of.the master oscillator by a given factor, in the ,example beingdescribed by a factorof three.

Upon reversal of the AC signal output of the master inverter circuit,one of the slave inverter circuits is prepared for actuation by asubsequent signal yfrom the common voscillator at the proper interval.For example, in the .example illustrated, where one-half cycle ofthecom- .mon oscillator represents 60 or 1/6 of the desired period or cycleof the youtput frequency, actuation ofthe switching .means of the secondinverter circuit one-half cycle .of the common oscillator output afterswitching ofthe kmaster inverter circuit will produce a 60 phase shiftin the AC output of the aforesaid slave inverter circuit rela- .tive tothe master inverter circuit output. A 60 phase shift is equivalent to a240 phase shift if the signal nvolved isiinverted by a properconnectionof the secondary windingof-.the inverter output transformer. Y

In a similar manner, where a three phase system Ais involved, the Athirdinverter circuit is responsive to the reversal of state of the outputofthe second inverter .circuit by preparing -the switching means foractuation ,one-half cycle .of the common .oscillator output afterswitchingvof .the second inverter circuit.

tOther aspects of the .invention to be described relate lto the .meansfor controlling or synchronizing the switchling means. These and otheraspects of the invention will vbecome apparent upon making referencetoVthe specificationto follow, Ythe claims and-the drawings wherein:

FIG. 1 is .a box diagram illustrating the `basic principal .of operationofthe present invention;

FIG. ,-2 vis a circuit diagram of one form of the present invention;

Vthree such inverter circuits 4A, 4B and 4C being shown in ythe.exemplary vcircuit of FIG. 1 /for providingthree sinusoidal signals S1,S2 and S3 which differ in phase from one another by The invertercircuits 4A, 4B

and 4C are synchronized to their desired frequency by a commontoscillator generally indicated by reference numeral 6. The output of theoscillator 6 is fed to inputs of all three inverter circuits and, asabove explained, has a frequency substantially higher than the desiredfrequency at the output of the phase inverter system. In the exemplarycircuit, the master oscillator is assumed to have a frequency of 1200cycles per second and the output frequency of the inverter system isassumed to be 400 cycles per second.4

Each phase inverter circuit is preferably a square wave oscillatorinverter circuit which has a free running frequency which is lower thanthe desired output frequency of the inverter system. The phase invertercircuit 4A, which is referred to as a master inverter circuit, acts as afrequency divider which provides a square wave output at the desiredoutput frequency synchronized by the output of the common oscillator.The output of the master inverter circuit 4A is fed to a filter 8A whichremoves all the frequencies but the fundamental frequency to produce asinusoidal output S1. If a square wave output was desired the filtercircuit 8A -would be omitted.

Each reversal of polarity of the output of the phase inverter circuit 4Ais fed through a synchronization prepare line 12 to an input of thefirst slave inverter circuit 4B. (Although the line 12 is shownextending from the same output line as the line extending to the ltercircuit 8A, it should be understood that this is a diagrammatic showingonly yand separate output windings of an output transformer of theinverter circuit, not shown in FIG. 1, would probably be used in apractical embodiment of the present invention.) This prepares the slaveinverter circuit 4B for synchronization by a subsequent pulsationreceived from the common oscillator 6, such as the next successive halfcycle pulsation of the common oscillator. In a similar way, when theslave inverter circuit 4B produces a reversal in the output thereof, anoutput signal is fed on a synchronization prepare line 12 to the otherslave inverter circuit 4C in the three phase system being described, forpreparing the same for a signal reversal operation upon receiving asubsequent pulsation from the master oscillator 6. In the case wheresine wave signals are desired, the square wave outputs of the slaveinverter circuits 4B and 4C are fed to lter circuits 8B and 8C whichlter out all but the fundamental sinusoidal signals from the square waveoutput signals involved.

FIG. 3 illustrates some of the waveforms present in the variousembodiments of the invention shown in the drawings. Thus, FIGS. 3a and3b show two outputs of the common oscillator 6. FIG. 3c illustrates thesquare Wave otuput of the master inverter circuit 4A on the same timebase as the common oscillator output of FIG. 3a. The solid line portionof FIG. 3d illustrates the square wave output of the slave invertercircuit 4B at the input of the output transformer thereof, and thedashed line portion of FIG. 3d represents a 180 inversion of the solidline waveform which provides a square wave having a 240 phasedisplacement with respect to the master inverter circuit output and isobtained at the output of the slave inverter output transformer. FIG. 3erepresents the output of the slave inverter circuit 4C having a 120phase relative to the output of the master inverter circuit 4A.

Refer now to FIG. 2 which illust-rates one exemplary form of the presentinvention. As there shown, the cornmon oscillator 6 is a square waveoscillator circuit of unique design which has the advantages ofsimplicity and reliability. The circuit illustrated utilizes a pair ofPNP transistors T1 and T2 whose collector electrodes are connected toopposite ends of the primary winding 12 of a transformer 14. The primarywinding 12 has a center tap point 13 to which a conductor 14 extendsconnected to a negative bus 17 leading to the negative terminal 16 ofthe source of direct current voltage 2. The lemitter electrodes of thetransistors T1 and T2 are connected by a conductor 18 to a bus 19leading to the positive terminal 20 of the source of direct currentvoltage 2.

The base electrode of the transistor T1 is connected through a resistor21 in parallel with a capacitor 23 to the bottom end of feedback winding12a. The other end of the winding 12a is connected to the line 18leading to the positive bus 19.

A feedback winding 12b is provided on the transformer 14 which windinghas a bottom end connected through a saturable reactor 26 to the baseelectrode of transistor T1. The upper end of the winding 12b isconnected to a terminal 31 which is connected to one end of a parallelcircuit comprising the anode and cathode or load terminals of a pair ofgated diodes 28 and 28' also referred to as silicon controlled rectiers.A resistor 29 is connected directly between the base electrode oftransistor T1 and the terminal 31. The transformer 14 has a feedbackwinding 12d, the upper end of which is connected through a resistor 21in parallel with a capacitor 23 to the base electrode of the transistorT2. The bottom end of the feedback winding 12d is connected to the line1S leading to the positive bus 19.

A pair of gated diodes 28 and 28 are provided having cathode and anodeelectrodes 32-34 and 32-34 connected in reverse relation between theaforementioned terminal 31 and a terminal 42 connected to the baseelectrode of the transistor T2. The anode and cathode electrodes of thegated diodes are connected in a loop circuit including the feedbackwindings 12b and 12d and the emitter to base circuit of the transistorT1 or T2 conducting at a given instant. The phases of the voltages inthe transformer windings 12b and 12d are always in additive relationshipto prepare one of the gated diodes 28 or 28' for conduction when thesaturable reactor 26 saturates, the gated diodes being respectively soprepared during successive half cycles of the oscillator output.Conduction of one of the gated diodes will couple the voltages of thewindings 12b andl 12d to the emitter base circuit of the conductingtransistor to render the same non-conductive.

The frequency at which the oscillator operates is determined by aresonant circuit including an inductance 36 and a capacitor 38 connectedin series with a feedback winding 12e` of the transformer 14. Thisseries circuit including the feedback winding, the inductance 36 andcapacitor 38 is connected between a line 35 connected to the controlelectrodes 30 and 30 of the gated diodes 28 and 28 and the terminal 31connected to the cathode electrode 32 of the gated diode 28 and theanode electrode 34 of the gated diode 28. The inductance and capacitorform a shock excitable resonant circuit which, in response to the steepwave front of the voltage induced in feedback winding 12C, produces asinusoidal current at the desired frequency of the oscillator. Theoscillator, in the absence of the gated diodes 28 and 28 and theassociated resonant circuit, would oscillate at a frequency slightlylower than the frequency to which the resonant circuit is tuned.

The polarity of the sinusoidal voltage present on the line 35 extendingto the control electrodes of the gated diodes will vary duringsuccessive half cycles of the oscillator output, and during a given halfcycle is of a proper polarity to fire the gated diode 28 or 28 whoseanode electrode is connected to a positive voltage from the feedbackwindings 12b and 12d. The gated diode 28 is a PNPN semi-conductorrequiring a positive voltage between its control and cathode electrodesto fire the same, while the gated diode 28 is a NPNP semi-conductorrequiring a negative voltage between the control and anode electrodesthereof to fire the same. It is thus apparent that the gated diodes 28and 28' can be fired only during successive half cycles of theoscillator output.

The over-all operation of the square wave oscillator circuit 6 may besummarized as follows, When power is initially turned on, one of thetransistors T1 or T2 will l start conducting first. Whichever transistorthis may be,

the resulting flow of current through the associated half of the primarywinding 12 will induce a voltage in the feedback windings 12a and 12dwhich, it will be noted,

' are connected in opposite sense between the base and emitterelectrodes of the associated transistors, so that the voltages inducedtherein will be in a direction to sustain the conduction of the first toconducttransistor and to render the other transistor non-conductive. Inthe absence of external synchronization, saturation of the core of thetransformer 14 will ultimately occur which results in the reversal ofthe voltage conditions of the transformer and the conductive states ofthe transistors. This free running oscillator action is overridden bythe synchronization action of the control circuit including the gateddiodes 28 andl 28 which are fired at a frequency higher than the freerunning frequency of the circuit under control of the shock excitableresonant circuit including the inductance 36 and capacitor 38.

The shock excitable resonant circuit produces a sinusoidal voltage inthe control circuits of the gated diodes at the desired frequency of theoscillator which voltage fires one of the gated diodes at the beginningof each half cycle of the oscillator output. When the polarity of thesinusoidal signal fed to the control electrodes 30 and 30 ofthe gateddiodes is positive, the voltage conditions on the anode and cathodeelectrodes of the gated diode 28 is sufficient toeffect the firing ofthe same upon saturation of the saturable reactor 26. When this occurs,the voltage conditions at the base electrodes of the transistors T1 andT2, due to the resulting couplingl of the loop circuit voltage referredto lbefore, will render the conducting transistor non-conductive andnon-conducting transistor conductive upon saturation of the saturablereactor 26. This will result in a reversal of the polarity of thevoltages induced in the transformer windings, which reversal will thenrender the conductive gated diode 28 or 28' nonconductive. In theabsence of the saturable reactor 26, hole storage would allow a reversecurrent in the latter gated diode and thus upset the switchingperformance. The saturable reactor 26 prevents the sudden reversal ofvoltage across the gated diode 28 or 28 as this reversal drives thesaturable core 26 from a saturated to an (momentary) unsaturatedcondition, which disrupts the feeding of energizing voltage to thelatter gated diode and stops current flow due to hole storage. Thisreversal of voltage prepares the previously non-conductive gated diodefor conduction as soon as the polarity of the voltage fed to the controlelectrode 30 or 30 thereof from the shock excited resonant circuitreverses. When the latter gated diode fires, this will effect anotherreversal of the oscillator circuit output which generates a new halfcycle of the square wave output.

The oscillator circuit described will produce square wave signals insecondary winding pairs 12e-12e', 12f- 121" and`12g-12g which are` 180out of phase as indicated in FIGS. 3a and 3b. The inverter circuits aresquare Wave inverter oscillator circuits which operate similarly to thecommon oscillatorvcircuit 6 except for the manner of synchronizationthereof. Thus, the inverter circuits 4A, 4B and 4C are interconnected insuch a way that they are synchronized at a sub-harmonic frequency of thecommon oscillator6 and produce signals displaced in phase from oneanother to provide the desired polyphase signal'output.

Inverter circuit 4A includes a pair of PNP transistors T3 and T4 havingcollector electrodes connected to opposite ends of a primary winding 50aof a transformer 51a. The primary winding 50a has a center tap pointconnectedto a conductor 54 extending to the negative bus 17. The emitterelectrodes of the transistors T3 and T4 are .connected to a line 58extending to the positive bus 19.

They transformer' 51a has feedback windings 52a and 53a which aresimilar in function' to the feedback windings 1'2afand 12d of the commonoscillator 6. The lower end of the feedback winding 52a is connectedthrough a resistor 61a to the base electrode of the transistor T3. Theupper end of the feedback winding 53a is connected through a resistor62ar to the base electrode of the transistor T4. The other ends of thewindings 52a and 53a are respectively connected to the positiveconductor 58 and to the positive bus 19.

As in the case of the common oscillator 6, the transistors T3v and T4will be rendered conductive during alternate half cycles of the desiredsquare wave output of the circuit involved and in so doing will couplethe source of direct current voltage in opposite directions through theprimary winding 50a during successive half cycles of the invertercircuit operation. The conductive states of the transistors T3 and T4are switched by a gated diode circuit which electrically connects thebase electrodes of the transistors T3 and T4 together through a feedbackwinding 54a.

The bottom end of the feedback Winding 54a is connected to the baseelectrode of the transistor T3 and the upper end thereof is connected tothe cathode and anode electrodes 64a and 73a', respectively, of a pairof reverse connected gated diodes 63a and 63a. The gated diode 63a is aPNPN type gated diode which requires a positive voltage between itscontrol and cathode electrodes 65a and 64a to fire the same and thegated diode 63a is an NPNP gated diode which requires a negative voltagebetween its control and anode electrodes 65a' and 73a' to fire the same.The bottom end of the feedback winding 54a is coupled to the controlelectrodes 65a and 65a of the respective gated diodes through asaturable core reactor 65a and a resistor 67a. A resistor 68ainterconnects the juncture of the reactor 65 and resistor 67a to thecathode and anode electrodes respectively of the gated diodes 63a and63a. v

It is apparent that the gated diodes 63a and 63a' will be prepared forfiring during alternate half cycles of the voltage induced in thewinding 54a upon saturation of the saturable reactor 65a which acts as agate which couplse the voltage of the transformer winding 54a to thecontrol electrodes of the gated diodes. The saturable reactor 65a isdesigned so that the reactor will not saturate upon reversal of thepolarity of the voltage in transformer winding 54a for a time intervalnot less than or more than 180 relative to the inverter circuit output,which is just before the third halfcycle of the oscillator output afterthe reversal takes place. In a manner to be more fully described, thisdelay action of the saturable reactor 65a produces a frequencydivide-bythree action in the inverter circuit which will result in thefiring of one of the gated diodes 63a or 63a every one and one-halfcycles (i.e., three half cycles) of the output of the common oscillator6.

The anode and cathode electrodes of the gated diodes 63a and 63a arerespectively connected in series current aiding relationship with theanode and cathode electrodes71a-75a and 71a-75a of an associated pair ofreverse connected PNPN gated diodes 69a and 69a' whose controlelectrodes 79a and 79a are coupled through resistors 81a and 81a'respectively to the secondary Windings 12e and 12e of the commonoscillator output transformer 14. The connections from the controlelectrodes of the gated diodes 69a and 69a to the transformer windings12e and 12e are such that the control electrodes will become positiveduring alternate half cycles of the common oscillator output. Thecathode electrode 71a of the gated diode 69a and the anode electrode 75aof gated diode 69a are connected by conductor 77 to the base electrodeof the transistor T4.

The gated diode connections descri'bedabove are such that the voltagesof the transformer windings 54a and 53a will always be applied involtage additive relation through the emitter and base electrodes of oneof the transistors T3 or'T4, and the resultant voltage will be in the'direction to render the gated diodes 63a-69a and 63a69a' conductiveduring alternate half cycles of the output of the inverter circuit whenthe saturable core 65a is satur ated and the higher frequency signal onthe control electrodes 79a or 79a is of the requisite polarity. Upon thefiring of either of the gated diode pairs 63a-69a or 63a- 69a, theconductive states of the associated transistors T3 and T4 will reverse.to initiate a new half cycle of the output of the inverter circuit.

The transformer 51a also has an output winding 83a for controlling theoperation of the slave inverter circuit 4B. In the exemplary embodimentof the invention being described, it will be recalled that the secondinverter circuit 4B is to generate a square wave 240 (or 60) out ofphase with respect to the output of the master inverter circuit 4A.

The master and slave inverter circuits have substantially identicalcomponents which have been similarly numbered except that an alphabetcharacter b or c has been added to the reference characters of the slaveinverter circuits 4B and 4C. One difference between the master and slaveinverter circuits is that the saturable reactor 65a of the masterinverter circuit saturates between a 120-l80 time interval relative tothe inverter output frequency while the saturable reactors 65b and 65Cof the slave inverter circuits become saturated in a time intervalrelated to the desired phasing of the slave inverter signals, namelyjust prior to the 60 point relative to the inverter output frequency, sothat the initiation'of the next pulsation of the common oscillatoroutput (which is coincident with the 60 point) will trigger the slaveinverter circuit involved.

The upper end of transformer winding 83a is connected to the cathode andanode electrodes respectively of a pair of gated diodes 63h and 63bwhich correspond to the gated diodes 63a and 63a' in the master invertercircuit 4A. The bottom end of the control winding 83a is connected tothe upper end of the feedback winding 54b of the output transformer 51bof the slave inverter circuit 4B. The bottom end of the winding 54h isconnected to the bottom terminal of the saturable reactor 65h. Thesaturable reactor 65b is located in a loop circuit which includesresistor 69b and the windings 83a and 54b of the transformers 51a and51b connected in series. The voltages in the transformer windings 83 and54h are in additive relation whenever the master inverter circuit outputreverses in polarity. The saturable reactor 65b will then be driven tosaturation within the 60 interval referred to, which couples the voltagein the windings 83a and 54b to the control electrodes of the gateddiodes 63h and 63h to prepare one of the same for firing when theassociated gated diodes 69b or 69b' receives the next pulsation from thecommon oscillator.

The relationshippbetween the slave inverter circuits 4B and 4C is thesame as the relationship between the master inverter circuit 4A and theslave inverter circuit 4B. Thus, the transformer 51b of the slaveinverter circuit 4B has a winding 83h which is connected to transformerwinding 54e and gated diodes 63C and 63C of the slave inverter circuitas described above in connection with master inverter circuit winding83a, slave inverter circuit winding 54]; and gated diodes 63b and 63h.The polarity of the output of the output of the slave inverter circuit4C will therefor reverse 60 after the reversal of the output of theslave inverter circuit 4B.

The outputs of the inverter circuits 4A, 4B and 4C shown in FIG. 2 aretaken across output windings 90a, 90b and 90e of transformers 51a, 51band 451C and will comprise three square wave signals which have arelative phasing of 120.

Refer now to the embodiment of the invention shown in FIGS. 4 and 4Awhich produces three amplitude regulated sinusoidal signals having arelative phasing of 120 and which has a slave inverter circuit 4B' and4C which operate without an upper pair of gated diodes like 63b- 63h'and 63c-63c and the associated saturable core re- 8 actors 6511 and 65Cpresent in the circuit of FIG. 2. The circuits of FIG. 2 and FIGS. 44Ahave many common elements which will be similarly numbered to avoidundue duplication of circuit description.

The phase inverter circuit shown in FIG. 4 includes a pulse widthmodulator circuit generally indicated by reference numeral whichprovides amplitude regulation. This circuit is interposed between thepositive terminal 20 of the source of direct current voltage 2 and thepositive bus 19. The circuit 100 includes a pair of PNP transistors T5and T6. The emitter electrode of the transistor T5 is connected to thepositive terminal 20 and the collector electrode thereof extends througha lter choke 104 to the positive bus 19. A filter capacitor 106 extendsbetween the output side of the filter choke 104 and a line 107 extendingto the negative terminal 16 of the source of direct current voltage 2. Arectifier 108 is connected between the input side of the choke 104 andthe line 107.

In a manner to be described, the transistor T5 is periodically renderednon-conductive for intervals such that the direct current output of thefilter circuit which energizes the inverter circuits will maintain apredetermined average sinusoidal voltage output with varying loadcurrent. The transistor T5 will be in a conductive state when power isinitially applied to the circuit upon closure of a switch 101 in serieswith the source of direct current voltage source 2. The circuitry forcontrolling the transistor T5 will now be described.

The base electrode of the transistor T5 is connected to the emitterelectrode of the transistor T6. The collector electrode of thetransistor T6 is connected to the collector electrode of the transistorT5. The base electrode of the transistor T5 is connected to the juncturepoint of the pair of resistors 110 and 112 whose opposite ends arerespectively connected to the emitter electrode of the transistor T5 andthe output terminal 114 of a magnetic amplifier switching circuitgenerally indicated by reference numeral 111 which is responsive to thesinusoidal output of the inverter system. The terminal 114 is connectedto the anode of a rectifier 115 in turn connected through a resistor 118to the base electrode of the transistor T6. A resistor 120 is connectedbetween the base electrode of the transistor T6 and the line 107 leadingto the negative terminal 16 of the source of direct current voltage 2.

From the circuit just described it is apparent that the transistor T5 isdriven by the current gain developed by the other transistor T6 whoseload circuit extends through the base circuit of the transistor T 5. Inthe absence of any voltage fed to the base circuits of the transistorsfrom the magnetic amplifier switching circuit 111, the voltagesdeveloped in the resistors 110, 112 and 120 by the flow of directcurrent from voltage source 2 will operate transistors T5 and T6 in ahighly conductive state which couples the direct current output of thevoltage source 2 to the positive bus 19 extending to the variousinverter circuits.

To cause the square wave inverter circuit 4A to start oscillating whenit is operated into a heavy load, a current is sent through the baseelectrodes of one of the transistors T3 and the transformer primarywinding 50a which will induce a voltage into the various windings of thetransformer so that the circuit will be regenerative. To this end, anelectronic switch in the form of a gated diode 123 is provided, theanode electrode 125 thereof being connected through a resistor 127 tothe base electrode of the transistor T3. The cathode electrode 129 ofthe gated diode is connected to the juncture of the upper end of theprimary winding 50a of the inverter output transformer 51a and thecollector electrode of transistor T3.

The control circuit for the gated diode 123 includes the resistor 61aand a resistor 130 connected in series between r the 'base electrode ofthe transistor T3 and the control electrode 133 of the gated diode 123.A capacitor 137 shunts the resistor 61a, and a rectifier 139 shunts theresistor 130, A back-biasing capacitor 140 is connected between theresistor 130 and the upper end of the primary winding 50a of thetransformer 51a.

When power is first applied to the circuit, it is apparent that apositive voltage will be applied to the control electrode 133 ofthegated diode 123 to effect the firing thereof to establish a circuitextending from the positive line 19, through the emitter and baseelectrodes of the transistor T3, resistor 127, anode and cathodeelectrodes of the gated diode 123 and the primary Winding 50a to thenegative bus 17. The resultant flow of base current will establish ahighly conductive condition between the emitter and collector electrodesof the transistor T3r to start the operation of the inverter circuit 4A.The resultant voltage induced in the winding 52a by the initiating ofthe conduction of the transistor T3 will make the bottom end of thefeedback winding 52 negative with respect to the upper end thereof tocontinue to maintain conduction of the transistor T3. When thetransistor T3 is fully conductive, the voltage conditions in the circuitwill be such that a voltage at the base electrode of transistor T3 willbe negative with respect to the voltage at the collector electrodethereof soy that the anode of the gated diode 123 will be negative withrespect to the cathode thereof to render thesame non-conductive. Thegated diode 123 must be .rendered nn-conductive after initial startingof the inverter circuit or else the gated diode will maintain thetransistor T3 in a conductive state. When the gated diode 123 isrendered nonconductive, the rectifier 139 will conductto charge thecapacitor 140 negative. When fthe transistor T3 becomes non-conductiveand the voltage conditions on the winding 52a reverse, the gated diode123 will be held in anon-conductive state by the back bias appliedthereto from the capacitor 140. The negative charge lost on thecapacitor 140 during the non-conduction of the transistor T3 is replacedduring the next half cycle when the rectifier 139 is conducting again.

The only other addition to the master inverter circuit 4A' worthy ofmention is the addition of reverse current bypass rectifiers 141 and 142respectively connected between the opposite ends of the primary winding50a and the positive line 58.

Since the inverter circuit 4A operates in substantially the same way asthe circuit 4A previously described, a further description of thiscircuit will not now be given.

As previously indicated, the slave inverter circuits 4B and 4C havegateddiode circuits which are much lsimpler than the gated diodecircuits' of the corresponding inverter circuits 4B and 4C in theembodiment of the invention shown in FIG. 2. The main difference betweenthese circuits is the omission of the upper pair of gated diodes 63b63band 63c-63c and their associated control circuits including thesaturable reactors 65b and 65C. The associated transformer windings 54band 54C are also omitted in the circuit of FIG. 4. This modification ismade possible 'bythe selection of a common oscillator frequency whichhas a period equal to the desired phasing of the signals produced by theinverter system which, in the three phase exemplary embodiment of theinvention being described, is 120. On the other hand, the invertersystem of FIG. 2 is operable with a wide variety of frequencies due tothe delay action obtainable with saturable reactorsV and the associatedgated diodes 63b\6'3b' and GSC-63C.

As illustrated in FIG. 4, the control winding 83a of the master invertercircuit 4A which controls' the operation of the slave inverter circuit4B has one'end connected directly to the base electrode of thetransistor T3b and another end connected to the cathode andl anodeelectrodes respectively of the PNPN gated diodes 69h and 69h associatedwith the oscillatork output transformer windings 12)c and 12]". Thephasing of the voltages in'- duced in the windings 12f and 12]" is suchthat, at the instant of reversal of the current in the winding 83a ofthe master inverter circuit transformer, the polarity of the square wave-contol voltages lfed to the contol electrodes 79b or 795' of the gateddiode prepared for firing is opposite to that required to fire the same.However, during the next successive half cycle of the common oscillator,the polarity of this voltage will be proper to fire the gated diodeinvolved.

The slave inverter circuit 4C is substantially the same circuit as theslave inverter circuit 4B' and responds to the reversal of current inthe control winding 83b of the slave inverter circuit 4B in the samemanner as just described With respect to the inverte circuit 4B', and soa further description thereof will not be given.

As in the case of the master inverter circuit 4A?, the slave invertercircuits 4B and 4C have reverse current bypass rectifiers 141b and 142b,and 141C and 142C.

As previously indicated, amplitude regulation is obtained by means ofcontrolling the off time periods of the transistor T5 in the pulse widthmodulation circuit 100 by means of the magnetic amplifier switchingcircuit 111. The magnetic amplifier switching circuit 111 is controlledby a voltage sensing circuit (FIG. 4A) including a full wave rectifiersection comprising a pair of rectifiers 152 and 152 connected betweenopposite ends of a secondary winding 154 of atransformer 156 and acommon point 158. A filter circuit comprising an inductance and acapacitance 162 are connected between the common point 158 and a line164 leading to the center tap of the transformer winding 154. The centertap is connected by a conductor 165 to the negative bus 107. The filtercircuit provides a direct current voltage which is proportional to theaverage value of a sinusoidal voltage induced in the winding 154 fromthe primary winding 166 of the transformer 156. This direct currentvoltage is developed across the capacitor 162 and is applied to a bridgecircuit 168 having a first branch comprising series connected resistors167 and 169 and a second branch connected in parallel with the firstbranch and comprising a resistor 171 and a Zener diode 173. The outputof the bridge circuit is taken across a pair of conductors 175 and 177connected respectively to the juncture of resistors 167 and'169 in oneof the branches and the resistor 171 and Zener diode 173 in the otherbranch. The Zener diode 173 provides a fixed reference voltage acrossthe Zener diode, and the resultant voltage appearing across theconductors 175 and 177 represents the difference between the Zener.diode voltage and the voltage across the resistor 169. This voltageconstitutes a control voltage fed by the conductors 175 and 177 to theterminals X and Y in the magnetic amplifier switchingcircuit 111 formingpart of they pulse width modulation circuit in FIG. 4. The magneticamplifier switching circuit includes a saturable core 111 having awinding 111a connected between the conductors 175 and 177. When theamplitude of the sinusoidal voltage fed 'to the voltage sensing circuitfrom transformer 156 is above a predetermined reference level, thebridge circuit output is unbalanced to feed direct current to themagnetic amplifier winding 111a in a direction which speeds up oradvances the saturation time of the saturable Core 111', and when theamplitude of this voltage is below this reference level the bridgecircuit output is unbalanced in the opposite direction to feed directcurrent to the `Winding 111a in a direction which slows down or delaysthe saturation time of the saturable core 111'.

The saturable core 111 has a pair of control windings 111b and 111Chaving one of their ends connected to the previously mentioned terminal114 connected to the base control circuit of the transistor T6, Theother ends of the windings 111i: and 111d are respectively coupled byrectifiers 180 and 180 to the opposite ends of a winding 12h of thecommon oscillator output transformer 14. The rectifiers 180 and 180 areso arranged in the circuit that they will couple a positive voltage orcurrent to the lefthand end of the magnetic amplifier windings 111b and111e during successive half cycles of the oscillator output.

The voltage coupled to these windings 111b and 111C will be effectivelycoupled to the base circuits of the transistors T5 and T6 to render themnon-conductive when the saturable core saturates. As above indicated,the timing of this saturation is a function of the amplitude of thesinusoidal voltage fed to the sensing circuit transformer 156.

In the exemplary circuit being described, the input to the voltagesensing circuit is obtained from an output winding 18311 of the outputtransformer 51a of the inverter circuit 4A across which winding onephase of the square wave output of the inverter system appears. Thewinding 183a is connected across the input of a conventional fltercircuit (FIG. 4A) generally indicated by reference numeral 18S whichfilters `out substantially all frequency components of the square waveoutputs induced in the latter windings except the fundamental sinusoidalcomponents thereof. As shown, the lter circuit 185 includes a number oftuned circuits which applies the fundamental sinusoidal component of thesquare wave thereof across the primary winding 166 of the sensingcircuit transformer 156.

Withthe pulse width modulation and voltage sensing circuits which aredescribed above, the non-conductive intervals of the transistors T5 andT6 will maintain at a fairly constant level the sinusoidal output of theinverter circuit provided the loads on the three phase outputs of theinverter system described remain at comparable values.

The'variously phased outputs of the master and slave inverter circuits4A', 4B and 4C appear across output windings 90a, 90b and 90C of thetransformers 51a, 51b and 51e, These windings may be interconnected inpairs, if desired, in a manner well known in the art to cancel out thirdharmonic components or, as in the simplied version of the outputcircuits shown in FIG. 4A, may be directly fed to the individual filtercircuits 8A, 8B and 8C. Also, if a Y three phase arrangement is desired,the outputs of the lter circuits may be connected through transformers(not shown) having output windings connected to provide a neutralconnection in addition to three output connections in a manner well knowin the art.

The present invention provides a highly effective and reliable invertersystem for providing polyphase square wave or sinusoidal signals yfromdirect current. The inverter system of the invention is designed toproduce a precise phasing of the inverter circuit outputs synchronizedby a common oscillator, and has the capability of providing appreciableamounts of power where this is desired.

It should be understood that numerous modifications may be made in thepreferred forms of the invention describes above without deviating fromthe broader aspects of the invention.

What I claim as new and desire to protect by Letters Patent of theUnited States is:

1. A polyphase inverter system operating from a source of DC voltage forgenerating a number of signals at a frequency f1 having respectivelydifferent phases, said circuit comprising: a .source of DIC voltage;master and slave inverter circui-ts for respectively generatingreference phase and dependen-t phase signals, each of the invertercircuits including an output transformer having primary and secondarywinding means, switch means for alternately coupling current from saidsource of DC voltage in opposite directions through said primary windingmeans upon successive a-ctuations thereof, wherein an AC signal isinduced in the secondary Winding means, the output transformer of eachinverter circuit having a saturable core and feedback and additionalwinding means thereon, said switch means of each inverter circuitcomprising electronic switching devices each with control and loadterminals, means connecting the feedback winding means of each outputtransformer with the control terminals of the associated switch meansfor forming a square wave multivibrator circuit with a free runningfrequency which is slightly lower than the desired -output frequency flof the inverter circuit and where the switch means are operated inopposite conductive states and reversal of the conductive state of oneof the switch means will trigger the multivibrator circuit to reversethe conductive states of the switch means; a common oscillator energizedfrom said source of DC voltage and providing a signal output forsynchronizing the actuation of said inverter switch means and having afrequency which is an integral number `of times higher than thefrequency fl; respective switch control means for con-trolling theactuation of the `switch means of the various inverter circuits in apredetermined time sequence at the frequency fl, the switch controlmeans of each inverter circuit including reverse parallel connectedgated diodes having control and load electrodes, the load electrodes ofthe gated diodes being -coupled to at least part of the additionalwinding means of the .associated out-put transformer to prepare adifferent one of the gated diodes for tiring each half cycle of theinverter circuit output and coupled to the control terminals of theassociated switch means to effect triggering of the multivibratorcircuit involved when one of the gates diodes is fired, and meanscoupling the output of said common oscillator to the control electrodesof the gated diodes of each inverter circuit; said switch control meansof each slave inverter circuit including switch operation prepare meansresponsive to the reversal of the AC .signal in the output of theinverter circuit which operates immediately ahead of it for preparingthe associated switch means for subsequent actuation by the output ofsaid common oscillator fed thereto, said switch operation prepare meansof each slave inverter cir-cuit including means coupling at least partof the additional winding means of the inverter circuit which operatesimmediately -ahead of it to prepare one of the gated diodes of the slaveinverter circuit involved for tiring by a subsequent half cycle of thecommon oscillator output; and the switch control means of said masterinverter circuit including frequency determining means operatingcompletely independently of the slave inverter circuits for effectingsuccessive actuation of the master inverter switch means independentlyof the slave inverter circuits at intervals encompass-ing apredetermined number of half cycles o-f the output of said commonoscillator, said frequency determining means including means fordelaying the effect of the voltage in the additional winding means ofthe master inverter circuit output transformer on the gated diodes ofthe master inverter circuit for several half cycles of the commonoscill-ator output.

2. The polyphase inverter system of claim 1 wherein said delaying meansof the frequency determining means -of the 4master inverter circuit is asaturable core device which vhas a gate winding connected between saidadditional winding means and the control electrodes of the gated diodes,the core device becoming saturated to pass the output of the invertercircuit involved when the instantaneous value of the output exceeds agiven value.

3. The polyphase inverter system of claim 1 wherein ea-ch invertercircuit has two pairs of reverse parallel connected gated diodes eachhaving load electrodes and a control electrode, the load electrodes ofthe correspondingly oriented gated diodes of the pair of gated diodesbeing connected in series circuit relation; said delaying mean-s lofsaidm-aster inverter circuit comprises a saturable core device having agate winding connected between said -additional Winding means and thecontrol electrodes of one of the pairs of parallel connected gateddiodes of the master inverter circuit which gate winding effectssaturation of the core device when the signal fed thereto exceeds agiven value t-o pass the signal to the control electrodes of theassociated gated diodes to prepare one of the gated diodes for ring insynchronism with the output of the common oscillator; and said switchoperation 13 prepare means of each slave inverter circuit comprises asaturable core device with a gate winding coupled between the output ofthe inverter circuit which opera-tes immediately ahe-ad of it and thecontrol electrodes of one of the pairs of parallel connected gateddiodes of the slave inverter circuit involved which gate winding effectssaturation of the core device when the signal fed thereto eX- ceeds agiven value to pass the signal to the control electrodes of theassociated gated diodes to prepare one of the gated diodes for ring insynchronism with the common oscillator output, the output of said commonoscillator being connected to the control elect-rodes of the other pairof parallel connected gated diodes associated vvith each invertercircuit .to re one of the same and trigger the ring of the correspondingprepared gated diode of the other pair of gated diodes.

4. A polyphase inverter system operating from a source of DC v-oltagefo-r generating a number of signals at a frequency f1 havingrespectively different phases, said circuit comprising: a source of DCvoltage; master and .slave inverter circuits for respectively generatingreference phase and dependent phase signals, each of the invertercircuits including an output transformer having primary and secondarywinding means, switch means for alternately coupling current from saidsource of `DC voltage in .opposite directions through said primaryWinding means upon successive actuations thereof, wherein an AC signalis induced in the secondary winding means; a common oscillator energizedfrom said source of DC voltage and providing a signal output forsynchronizing the actuation of said inverter switch means and having afrequency which is an integral numbe-r of times higher than thefrequency fl; respective switch control means for con-trolling t-heactuation o-f the .switch means of the various inverter circuits in apredetermined time sequence at the frequency f1; the switch contr-olmeans of each slave inverter circuit including switch operation preparemeans responsive to the reversal of the AC signal in the output of theinverter circuit which operates immediately ahead of it for preparingthe associated switch means for subsequent actuation by the output ofsai-d common oscillator fed thereto, said switch operation prepare meansof each slave inverter circuit including a saturable core device with agate winding .coupled to the output of the inverter circuit whichoperates immediately ahead of it, the core device .sat-urating to passthe signal to the slave inverter circuit involved after a predetermineddelay period to prepare the same for actuation by the next cycle of theoutput of said common oscillator occurring after said delay period; .andthe switch control ymeans of said master inverter circuit includingfrequency determining means operating completely .independent-ly of theslave inverter circuits for effecting successive actuation of the masterinverter switch means independently of the slave inverter circuits atinterv-als encompassing a predetermined number of half 'cycles of theoutput of said common oscillator.

5. A polyphase inverter system .for generating a number of signals at afrequency f-l having respectively dilferent phases, said circuitcomprising: master and slave inverter circuits for respectivelygenerating alternating polarity reference phase and dependent phasesignals, each of said inverter circuits including switch means to besynchronized by an externally generated signal, a common oscillatorproviding an alternating polarity synchronizing signal output coupled tosaid switch means for synchronizing the actuation thereof and having .afrequency which lis an integral number of times higher than thefrequency f1, respective switch control means for actuating said switchmeans of the various inverter circuits in a predetermined time sequenceat the frequency f1, said switch control means of each slave invertercircuit incl-uding switch operation prepare means responsive to thereversal of the output of the inverter circuit which operatesimmediately ahead of it for preparing the associated switch means forsubsequent actuation by the output of said common oscillator fedthereto, said switch control means of said master inverter circuitincluding rfrequency-determining means operating completelyindependently of the slave inverter` circuits for eifecting successiveactuation of the associated switch means independently of the slaveinverter circuits at intervals encompassing a predetermined number ofhalf cycles of the output of said common oscillator, said frequencydetermining means including dclay means responsive to each reversal ofthe AC signal in the output of the master inverter circuit for preparingthe master inverter switch means for actuation by the next cycle of theoutput of said common oscillator after a predetermined delay periodafter said output reversal.

6. A polyphase inverter system for generating a number of signals .at afrequency f1 having respectively different phases, said circuitcomprising: master and slave inverter circuits for respectivelygenerating alternating polarity reference phase and depen-dent phasesignals, each .of said inverter circuits including switch means to besynchronized by an externally generated signal, a common oscillatorproviding an alternating polarity synchronizing signal output c-oupledto said switch means for synchronizing the actuation thereof and havinga frequency which is an integral number of times higher than thefrequency f1, respective switch control means for actuating said switchmeans of the various inverter circuits in a predetermined time sequenceat the frequency f1, said switch control means of each slave inver-tercircuit including .switch operation prepare means responsive to thereversal of the output of the inverter circuit which operatesimmediately ahead of it for preparing the associated switch means forsubsequent actu-ation by the output of said common oscillator fedthereto, said switch control means of said master inverter circuitincluding frequency-determining means operating completelyrindependently of the slave inverter circuits for effecting successiveactuation of the associated switch means independently of the slaveinverter circuits at intervals encompassing a predetermined number ofhalf cycles of the -output of said common oscillator, gating means -forcontrolling the feeding of Ithe output of said common oscillator to themaster inverter switch means, and said fre quency determining meansincluding delay means responsive to each reversal of the AC signal inthe output of the master inverter circuit by closing said gating meansafter a predetermined delay period after said output reversal to enablethe next cycle of the output of the common oscillator to actuate saidmaster inverter switch means.

References Cited UNITED STATES PATENTS 2,824,274 2/1958' Holt 321-18 X2,916,687 12/1959 Cronin 321-5 3,060,363 10/1962' Jensen 321-5 3,136,9576/1964 Putko-vich et al 321-5 X 3,207,972 9/1965' Love 321-5 JOHN F.COUCH, Primary Examiner. W. SHOOP, Assistant Examiner.

1. A POLYPHASE INVERTER SYSTEM OPERATING FROM A SOURCE OF DC VOLTAGE FORGENERATING A NUMBER OF SIGNALS AT A FREQUENCY F1 HAVING RESPECTIVELYDIFFERENT PHASES, SAID CIRCUIT COMPRISING: A SOURCE OF DC VOLTAGE;MASTER AND SLAVE INVERTER CIRCUITS FOR RESPECTIVELY GENERATING REFERENCEPHASE AND DEPENDENT PHASE SIGNALS, EACH OF THE INVERTER CIRCUITSINCLUDING AN OUTPUT TRANSFORMER HAVING PRIMARY AND SECONDARY WINDINGMEANS, SWITCH MEANS FOR ALTERNATELY COUPLING CURRENT FROM SAID SOURCE OFDC VOLTAGE IN OPPOSITE DIRECTIONS THROUGH SAID PRIMARY WINDING MEANSUPON SUCCESSIVE ACTUATIONS THEREOF, WHEREIN AN AC SIGNAL IS INDUCED INTHE SECONDARY WINDING MEANS, THE OUTPUT TRANSFORMER OF EACH INVERTERCIRCUIT HAVING A SATURABLE CORE AND FEEDBACK AND ADDITIONAL WINDINGMEANS THEREON, SAID SWITCH MEANS OF EACH INVERTER CIRCUIT COMPRISINGELECTRONIC SWITCHING DEVICES EACH WITH CONTROL AND LOAD TERMINALS, MEANSCONNECTING THE FEEDBACK WINDING MEANS OF EACH OUTPUT TRANSFORMER WITHTHE CONTROL TERMINALS OF THE ASSOCIATED SWITCH MEANS FOR FORMING ASQUARE WAVE MULTIVIBRATOR CIRCUIT WITH A FREE RUNNING FREQUENCY WHICH ISSLIGHTLY LOWER THAN THE DESIRED OUTPUT FREQUENCY F1 OF THE INVERTERCIRCUIT AND WHERE THE SWITCH MEANS ARE OPERATED IN OPPOSITE CONDUCTIVESTATES AND REVERSAL OF THE CONDUCTIVE STATE OF ONE OF THE SWITCH MEANSWILL TRIGGER THE MULTIVIBRATOR CIRCUIT TO REVERSE THE CONDUCTIVE STATESOF THE SWITCH MEANS; A COMMON OSCILLATOR ENERGIZED FROM SAID SOURCE OFDC VOLTAGE AND PROVIDING A SIGNAL OUTPUT FOR SYNCHRONIZING THE ACTUATIONOF SAID INVERTER SWITCH MEANS AND HAVING A FREQUENCY WHICH IS ANINTEGRAL NUMBER OF TIMES HIGHER THAN THE FREQUENCY F1; RESPECTIVE SWITCHCONTROL MEANS FOR CONTROLLING THE ACTUATION OF THE SWITCH MEANS OF THEVARIOUS INVERTER CIRCUITS IN A PREDETERMINED TIME SEQUENCE AT THEFREQUENCY F1, THE SWITCH CONTROL MEANS OF EACH INVERTER CIRCUITINCLUDING REVERSE PARALLEL CONNECTED GATED DIODES HAVING CONTROL ANDLOAD ELECTRODES, THE LOAD ELECTRODES OF THE GATED DIODES BEING COUPLEDTO AT LEAST PART OF THE ADDITIONAL WINDING MEANS OF THE ASSOCIATEDOUTPUT TRANSFORMER TO PREPARE A DIFFERENT ONE OF THE GATED DIODES FORFIRING EACH HALF CYCLE OF THE INVERTER CIRCUIT OUTPUT AND COUPLED TO THECONTROL TERMINALS OF THE ASSOCIATED SWITCH MEANS TO EFFECT TRIGGERING OFTHE MULTIVIBRATOR CIRCUIT INVOLVED WHEN ONE OF THE GATES DIODES ISFIRED, AND MEANS COUPLING THE OUT PUT OF SAID COMMON OSCILLATOR TO THECONTROL ELECTRODES OF THE GATED DIODES OF EACH INVERTER CIRCUIT; SAIDSWITCH CONTROL MEANS OF EACH SLAVE INVERTER CIRCUIT INCLUDING SWITCHOPERATION PREPARE MEANS RESPONSIVE TO THE REVERSAL OF THE AC SIGNAL INTHE OUTPUT OF THE INVERTER CIRCUIT WHICH OPERATES IMMEDIATELY AHEAD OFIT FOR PREPARING THE ASSOCIATED SWITCH MEANS FOR SUBSEQUENT ACTUATION BYTHE OUTPUT OF SAID COMMON OSCILLATOR FED THERETO, SAID SWITCH OPERATIONPREPARE MEANS OF EACH SLAVE INVERTER CIRCUIT INCLUDING MEANS COUPLING ATLEAST PART OF THE ADDITIONAL WINDING MEANS OF THE INVERTER CIRCUIT WHICHOPERATES IMMEDIATELY AHEAD OF IT TO PREPARE ONE OF THE GATED DIODES OFTHE SLAVE INVERTER CIRCUIT INVOLVED FOR FIRING BY A SUBSEQUENT HALFCYCLE OF THE COMMON OSCILLATOR OUTPUT; AND THE SWITCH CONTROL MEANS OFSAID MASTER INVERTER CIRCUIT INCLUDING FREQUENCY DETERMINING MEANSOPERATING COMPLETELY INDEPENDENTLY OF THE SLAVE INVERTER CIRCUITS FOREFFECTING SUCCESSIVE ACTUATION OF THE MASTER INVERTER SWITCH MEANSINDEPENDENTLY OF THE SLAVE INVERTER CIRCUITS AT INTERVALS ENCOMPASSING APREDETERMINED NUMBER OF HALF CYCLES OF THE OUTPUT OF SAID COMMONOSCILLATOR, SAID FREQUENCY DETERMINING MEANS INCLUDING MEANS FORDELAYING THE EFFECT OF THE VOLTAGE IN THE ADDITIONAL WINDING MEANS OFTHE MASTER INVERTER CIRCUIT OUTPUT TRANSFORMER ON THE GATED DIODES OFTHE MASTER INVERTER CIRCUIT FOR SEVERAL HALF CYCLES OF THE COMMONOSCILLATOR OUTPUT.